As integrated circuit devices advance to technology nodes at ever-smaller sizes, various components within these devices have also become smaller. Additionally, spacing between these components has decreased, creating challenges in layout formation and device optimization.
One integrated circuit device where shrinking dimensions play a role is the fin-shaped field effect transistor (also referred to as a finFET). The conventional finFET is a three-dimensional transistor structure that includes a set (e.g., one or more) of fin-shaped (relatively thin) source and drain regions overlying a substrate, and at least one (relatively thick) gate overlying the fin(s). The channel region in this finFET spans between the source and drain in the thin fin, beneath the gate. In one particular type of finFET, known as the replacement gate (RG) finFET, the fin (source-drain region) is formed prior to the gate.
It is known in the art that modifying a threshold voltage (Vt) of an integrated circuit device can enhance performance characteristics of that device. Conventional approaches for modifying a threshold voltage in finFET devices, e.g., RG finFETS, involve doping portions of the device to enhance channel mobility, or modifying the length of the channel region. Both of these approaches involve process steps such as masking, lithography and etching, which can complicate fabrication and consume time and resources.